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Disambiguation of "Lee, Chung-Len"

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A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.

, , , , , and . ISCAS, page 3426-3429. IEEE, (2008)

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Chung-Ho Lee

Chung-Yung Lee

Chung-Tien Lee

Anna-Len Nieschalk

Hsiang-len Tseng

 

Other publications of authors with the same name

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 306-311 (2009)Identifying invalid states for sequential circuit test generation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1025-1033 (1997)A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model., , and . J. Inf. Sci. Eng., 15 (6): 885-897 (1999)Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits., and . J. Inf. Sci. Eng., 16 (5): 687-702 (2000)An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits., and . Asian Test Symposium, page 173-178. IEEE Computer Society, (1999)A programmable multiple-sequence generator for BIST applications., and . Asian Test Symposium, page 279-285. IEEE Computer Society, (1995)An On-Chip Jitter Measurement Circuit for the PLL., and . Asian Test Symposium, page 332-335. IEEE Computer Society, (2003)Finite State Machine Synthesis for At-Speed Oscillation Testability., , , , and . Asian Test Symposium, page 360-365. IEEE Computer Society, (2005)A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC., , and . Asian Test Symposium, page 58-61. IEEE Computer Society, (2004)Multilevel full-chip routing with testability and yield enhancement., , , , and . SLIP, page 29-36. ACM, (2005)