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Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks.

, , , , , , , and . IEEE Access, (2021)

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Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal., , , and . ISCAS (4), page 334-337. IEEE, (2001)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)A reusable IP FFT core for DSP applications., , , , , , and . ISCAS (3), page 621-624. IEEE, (2004)A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., , and . ISCAS, IEEE, (2006)A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs., and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 211-231. Springer, (2008)A low-cost fault tolerant solution targeting commercial FPGA devices., and . J. Syst. Archit., 59 (10-D): 1255-1265 (2013)Automated Physics-Derived Code Generation for Sensor Fusion and State Estimation., , , and . CoRR, (2020)FPGA Acceleration of Approximate KNN Indexing on High- Dimensional Vectors., , and . ReCoSoC, page 59-65. IEEE, (2019)BLonD++: performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies., , , and . SAMOS, page 123-130. ACM, (2018)