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Disambiguation of "Shirahama, Hirokatsu"

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Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

, , , , and . ISMVL, page 43. IEEE Computer Society, (2007)

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Other publications of authors with the same name

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip., , , and . IEICE Trans. Inf. Syst., 97-D (9): 2304-2311 (2014)Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits., , , and . ISMVL, page 14. IEEE Computer Society, (2006)Energy-aware current-mode inter-chip link for a dependable GALS NoC platform., , , and . ISCAS, page 1865-1868. IEEE, (2014)Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry., , and . IEICE Trans. Electron., 90-C (4): 683-691 (2007)Design of High-Performance Quaternary Adders Based on Output-Generator Sharing., and . ISMVL, page 8-13. IEEE Computer Society, (2008)Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic., , and . IEICE Trans. Electron., 89-C (11): 1591-1597 (2006)High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs., , , , , and . IEICE Trans. Inf. Syst., 97-D (6): 1546-1556 (2014)Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link., , and . ISMVL, page 67-72. IEEE Computer Society, (2014)Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor., , , , and . ISMVL, page 43. IEEE Computer Society, (2007)Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link., , , and . APCCAS, page 683-686. IEEE, (2014)