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Disambiguation of "Piestrak, Stanislaw J."

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Design of an RNS reverse converter for a new five-moduli special set.

, , , , and . ACM Great Lakes Symposium on VLSI, page 67-70. ACM, (2012)

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Stanislaw Andruszewicz

Stanislaw Schmidt

Stanislaw Slowinski

Stanislaw Przerembel

Stanislaw Brehm

 

Other publications of authors with the same name

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units., and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (5): 1031-1039 (2017)Design of reverse converters for the general RNS 3-moduli set 2k, 2n - 1, 2n + 1., and . EURASIP J. Adv. Signal Process., 2023 (1): 92 (December 2023)The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes.. FTCS, page 457-464. IEEE Computer Society, (1990)Design of cost-efficient multipliers modulo 2a-1.. ISCAS, page 4093-4096. IEEE, (2010)Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor., , and . IEEE Trans. Computers, 62 (6): 1179-1192 (2013)Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels., and . J. Signal Process. Syst., 90 (3): 323-339 (2018)Design of Reverse Converters for a New Flexible RNS Five-Moduli Set 2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1 (n Even)., and . CSSP, 36 (11): 4593-4614 (2017)Error recovery technique for coarse-grained reconfigurable architectures., , , and . DDECS, page 441-446. IEEE Computer Society, (2011)On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.. DSD, page 133-140. IEEE Computer Society, (2010)Design of the coarse-grained reconfigurable architecture DART with on-line error detection., , , and . Microprocess. Microsystems, 38 (2): 124-136 (2014)