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Disambiguation of "Komoku, Kiyotaka"

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3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array.

, , , , , and . ISOCC, page 199-200. IEEE, (2016)

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Kiyotaka Yasuda

 

Other publications of authors with the same name

Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (2): 441-446 (2018)3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array., , , , , and . ISOCC, page 199-200. IEEE, (2016)Development support software of cell array processor and its neural network application., , , , and . IJCNN, page 2452-2455. IEEE, (1999)A study of current-reuse 800 MHz/1.9 GHz concurrent dual-band amplifier., , , , , and . RWS, page 245-247. IEEE, (2016)Interpolation Based Unbounded Model Checking for Time Petri Nets., , , , , and . GCCE, page 619-623. IEEE, (2018)Implementation of cell array neuro-processor by using FPGA., , , , and . IJCNN, page 2447-2451. IEEE, (1999)28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)A CMOS Temperature Sensor Circuit., , , , , and . IEICE Trans. Electron., 90-C (4): 895-902 (2007)A Test Structure to Analyze Electrical CMOSFET Reliabilities between Center and Edge along the Channel Width., , , , , and . IEICE Trans. Electron., 90-C (2): 515-522 (2007)