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3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison.

, , and . IEEE Trans. Computers, 71 (6): 1305-1319 (2022)

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An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors., , , and . IEEE Trans. Parallel Distributed Syst., 28 (6): 1564-1577 (2017)A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches., , and . IEEE Trans. Reliab., 69 (2): 594-610 (2020)Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes., , and . IEEE Access, (2024)Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors., , , and . EDCC, page 218-226. IEEE Computer Society, (2012)Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches., , , and . EDCC, page 120-129. IEEE Computer Society, (2016)3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison., , and . IEEE Trans. Computers, 71 (6): 1305-1319 (2022)ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories., , , and . IEEE Trans. Computers, 70 (4): 640-654 (2021)A link adaptation scheme for reliable downlink communications in narrowband IoT., and . Microelectron. J., (2021)Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits., , , and . J. Supercomput., 75 (7): 3945-3974 (2019)In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors., , and . ACM Trans. Design Autom. Electr. Syst., 20 (4): 61:1-61:28 (2015)