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Disambiguation of "Bacivarov, Iuliana"

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Fast worst-case peak temperature evaluation for real-time applications on multi-core systems.

, , , and . LATW, page 1-6. IEEE Computer Society, (2012)

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Iuliana Hofmann

Iuliana Lupu

Iuliana Bocancia

Anca-Iuliana Bonciocat

Roxana-Iuliana Teodor

 

Other publications of authors with the same name

PRO3D: programming for future 3D manycore architectures., , , , , , and . INA-OCMC@HiPEAC, page 47-50. ACM, (2012)Multiprocessor SoC software design flows., , , and . IEEE Signal Process. Mag., 26 (6): 64-71 (2009)ChronoSym: a new approach for fast and accurate SoC cosimulation., , , and . Int. J. Embed. Syst., 1 (1/2): 103-111 (2005)Worst-case temperature analysis for different resource models., , , and . IET Circuits Devices Syst., 6 (5): 297-307 (2012)Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration., , , , and . ASP-DAC, page 969-972. ACM Press, (2005)Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer., , , , and . DATE, page 10550-10555. IEEE Computer Society, (2003)Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application., , , , and . DATE Designers' Forum, page 166-171. European Design and Automation Association, Leuven, Belgium, (2006)Timed HW-SW cosimulation using native execution of OS and application SW., , and . HLDVT, page 51-56. IEEE Computer Society, (2002)Multi-Level Software Validation for NoC., , , , , and . Networks on Chip, Kluwer / Springer, (2003)Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms., , , , , , , , , and 11 other author(s). J. Syst. Archit., (2016)