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A linear time algorithm for optimal CMOS functional cell layouts.

, and . ICCD, page 449-453. IEEE Computer Society, (1990)

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A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays., , and . Discret. Appl. Math., 90 (1-3): 195-221 (1999)A New Approach to Online FPGA Placement., , , , and . CISS, page 145-150. IEEE, (2006)Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems., , and . EURASIP J. Adv. Signal Process., 2003 (6): 565-579 (2003)Exact algorithms for multilayer topological via minimization., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (11): 1165-1173 (1989)A New Model for Over-The-Cell Channel Routing with Three Layers., , , and . ICCAD, page 432-435. IEEE Computer Society, (1991)Logic foundry: rapid prototyping of FPGA-based DSP systems., , and . ASP-DAC, page 374-381. ACM, (2003)Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays., , , and . ICCAD, page 428-431. IEEE Computer Society / ACM, (1994)A simple and effective greedy multilayer router for MCMs., , and . ISPD, page 67-72. ACM, (1997)Via Minimization for Gridless Layouts., , and . DAC, page 159-165. IEEE Computer Society Press / ACM, (1987)A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology., , , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 665-674. Springer, (2000)