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Disambiguation of "Lee, Ching-En"

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An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration.

, and . ACSSC, page 747-751. IEEE, (2015)

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Ching-hua Lee

Kong-Ching Lee

Ching-Lung Lee

Wilhelm Ching

Paisal Chingduang

 

Other publications of authors with the same name

Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA., , , , and . CoRR, (2018)Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA., , , , and . FPGA, page 306. ACM, (2019)A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification., , , and . IEEE J. Solid State Circuits, 54 (7): 2081-2090 (2019)A total standard WIP estimation method for wafer fabrication., and . Eur. J. Oper. Res., 131 (1): 78-94 (2001)An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration., and . ACSSC, page 747-751. IEEE, (2015)VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters., , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS., , , , , and . VLSI Circuits, page 306-. IEEE, (2019)Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication., , , , , , , and . SiPS, page 1-6. IEEE, (2015)VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters., , , , , and . IEEE J. Solid State Circuits, 57 (11): 3490-3502 (2022)SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference., , , , , and . IEEE J. Solid State Circuits, 56 (2): 636-647 (2021)