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Disambiguation of "Kibune, Masaya"

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A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.

, , , , , , , , and . IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)

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Other publications of authors with the same name

A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS., , , and . ISSCC, page 436-438. IEEE, (2011)A Reference-Less Single-Loop Half-Rate Binary CDR., , , and . IEEE J. Solid State Circuits, 50 (9): 2037-2047 (2015)A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid., , , , , and . ISSCC, page 2102-2111. IEEE, (2006)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 45 (10): 2016-2029 (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 93-C (3): 295-302 (2010)A CMOS multichannel 10-Gb/s transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2094-2100 (2003)Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies., , , , , , and . IEICE Trans. Electron., 89-C (3): 300-313 (2006)An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 46 (12): 3140-3149 (2011)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers., , , , , and . CICC, page 1-4. IEEE, (2010)