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Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.

, , , , , and . J. Signal Process. Syst., 62 (3): 373-382 (2011)

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Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores., , , , , , and . J. Signal Process. Syst., 51 (3): 269-288 (2008)Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools., , , , , and . J. Signal Process. Syst., 62 (3): 373-382 (2011)Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors., , , , , , , , , and . RTCSA, page 215-222. IEEE Computer Society, (2006)Compiler Supports and Optimizations for PAC VLIW DSP Processors., , , , , , , and . LCPC, volume 4339 of Lecture Notes in Computer Science, page 466-474. Springer, (2005)Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files., , and . J. Supercomput., 61 (3): 1024-1047 (2012)Achieving spilling-friendly register file assignment for highly distributed register files., , , and . J. Supercomput., 69 (3): 1342-1362 (2014)Programming model and tools for embedded multicore systems., , , , and . Int. J. Embed. Syst., 4 (3/4): 259-269 (2010)Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files., , and . LCPC, volume 4382 of Lecture Notes in Computer Science, page 251-266. Springer, (2006)Register spilling via transformed interference equations for PAC DSP architecture., , and . Concurr. Comput. Pract. Exp., 26 (3): 779-799 (2014)