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Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence., and . FPL, page 225-233. IEEE, (2021)Object-Attribute Biclustering for Elimination of Missing Genotypes in Ischemic Stroke Genome-Wide Data., , , , , , , , and . AIST (Supplement), volume 1357 of Communications in Computer and Information Science, page 185-204. Springer, (2020)Finding a Needle in the Haystack of Hardened Interconnect Patterns., , and . FPL, page 31-37. IEEE, (2019)Detailed Placement for Dedicated LUT-Level FPGA Interconnect., , and . ACM Trans. Reconfigurable Technol. Syst., 15 (4): 37:1-37:33 (2022)Regularity Matters: Designing Practical FPGA Switch-Blocks., and . FPGA, page 99-109. ACM, (2023)NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs., , and . FPGA, page 11-22. ACM, (2021)IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck., , , , and . ICCAD, page 1-9. IEEE, (2023)Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths., , and . FPL, page 153-161. IEEE, (2020)Global Is the New Local: FPGA Architecture at 5nm and Beyond., , , and . FPGA, page 34-44. ACM, (2021)Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing., , and . FPGA, page 150-160. ACM, (2020)