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Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA.

, , , and . IEEE International Workshop on Rapid System Prototyping, page 179-185. IEEE Computer Society, (2003)

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Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study., , , and . GLOBECOM, page 2513-2519. IEEE, (2004)Structured Parallel Architecture for Displacement MIMO Kalman Equalizer in CDMA Systems., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (2): 122-126 (2007)An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture., , , and . EURASIP J. Adv. Signal Process., (2006)Reduced QRD-M detector in MIMO-OFDM systems with partial and embedded sorting., and . GLOBECOM, page 6. IEEE, (2005)Matlab as a development environment for FPGA design., and . DAC, page 607-610. ACM, (2005)Rapid prototyping and VLSI exploration for 3g/4G MIMO wireless systems using integrated catapult-c methodology., and . WCNC, page 958-963. IEEE, (2006)FFT-accelerated iterative MIMO chip equalizer architecture for CDMA downlink., , and . ICASSP (3), page 1005-1008. IEEE, (2005)Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems., , and . ISCAS (4), page 77-80. IEEE, (2004)Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes., , , and . ICASSP (4), page 225-228. IEEE, (2006)Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology., , , and . EURASIP J. Embed. Syst., (2006)