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A flexible DSP block to enhance FPGA arithmetic performance., , , , , and . FPT, page 70-77. IEEE Computer Society, (2009)Improving FPGA Performance for Carry-Save Arithmetic., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (4): 578-590 (2010)Fast INC-XOR codec for low-power address buses., , , and . IET Comput. Digit. Tech., 1 (5): 625-626 (2007)Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs., , , , , , , and . FPGA, page 181-190. ACM, (2008)Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs., and . FPL, page 225-231. IEEE Computer Society, (2011)A novel FPGA logic block for improved arithmetic performance., , and . FPGA, page 171-180. ACM, (2008)Efficient synthesis of compressor trees on FPGAs., , and . ASP-DAC, page 138-143. IEEE, (2008)Enhancing FPGA Performance for Arithmetic Circuits., , , and . DAC, page 334-337. IEEE, (2007)Reducing the cost of floating-point mantissa alignment and normalization in FPGAs., , , , , and . FPGA, page 255-264. ACM, (2012)Reducing the pressure on routing resources of FPGAs with generic logic chains., , , and . FPGA, page 237-246. ACM, (2011)