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A high-performance hardware implementation of the H.264 simplified 8×8 transformation and quantization video coding., , and . ICASSP (2), page 1137-1140. IEEE, (2005)Application of the residue number system to computer processing of digital signals., and . IEEE Symposium on Computer Arithmetic, page 220-225. IEEE Computer Society, (1978)Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1141-1150 (2008)A New Design Technique for Column Compression Multipliers., , and . IEEE Trans. Computers, 44 (8): 962-970 (1995)Implementation of a Simulation Engine for Clocked Molecular QCA., , and . CCECE, page 2128-2131. IEEE, (2006)Error Recovery in Continuous Valued Number System., , and . Journal of Circuits, Systems, and Computers, 20 (8): 1449-1476 (2011)VLSI Implementation of Complex Digitial Signal Processing Structures., , and . IAS, page 313-321. North-Holland, (1986)DBNS addition using cellular neural networks., , , and . ISCAS (4), page 3914-3917. IEEE, (2005)New Concepts for the Design of Carry Lookahaead Adders., , , and . ISCAS, page 1837-1840. IEEE, (1993)A hybrid DBNS processor for DSP computation., , , , , and . ISCAS (1), page 5-8. IEEE, (1999)