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Byte and modulo addressable parallel memory architecture for video coding.

, , and . IEEE Trans. Circuits Syst. Video Techn., 14 (11): 1270-1276 (2004)

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Configurable parallel memory architecture for multimedia computers., , , and . J. Syst. Archit., 47 (14-15): 1089-1115 (2002)On Design of Parallel Memory Access Schemes for Video Coding., , and . J. VLSI Signal Process., 40 (2): 215-237 (2005)Parallel memory architectures for video coding.. University of Tampere, Finland, (2004)base-search.net (ftunivtampere:oai:trepo.tuni.fi:10024/114794).Verifying external data memory interface for H.263 video DSP with memory simulator., , , and . EUSIPCO, page 1-4. IEEE, (2000)Parallel Memories in Video Encoding., and . Data Compression Conference, page 552. IEEE Computer Society, (1999)Parallel Memory Architecture for TTA Processor., , , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 273-282. Springer, (2007)Byte and modulo addressable parallel memory architecture for video coding., , and . IEEE Trans. Circuits Syst. Video Techn., 14 (11): 1270-1276 (2004)Scalable Parallel Memory Architectures for Video Coding., and . VLSI Signal Processing, 38 (2): 173-199 (2004)Parallel Memory Architecture for Application-Specific Instruction-Set Processors., , , and . J. Signal Process. Syst., 57 (1): 21-32 (2009)Parallel, memory access schemes for H.263 encoder., , , , and . ISCAS, page 691-694. IEEE, (2000)