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Disambiguation of "Ito, Hideo"

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Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core.

, and . DFT, page 503-510. IEEE Computer Society, (2003)

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Hideo Baba

Nobutaka Ito

Takao Ito

Akio Ito

Hisao Ito

 

Other publications of authors with the same name

Proposal of Testable Multi-Context FPGA Architecture., and . IEICE Trans. Inf. Syst., 89-D (5): 1687-1693 (2006)Redundant Design for Wallace Multiplier., and . IEICE Trans. Inf. Syst., 89-D (9): 2512-2524 (2006)X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability., and . IEICE Trans. Inf. Syst., 88-D (7): 1662-1670 (2005)A Checkpointing Method with Small Checkpoint Latency., , and . IEICE Trans. Inf. Syst., 91-D (3): 857-861 (2008)Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths., , and . IEICE Trans. Inf. Syst., 92-D (3): 433-442 (2009)Design for Delay Fault Testability of 2-Rail Logic Circuits., , and . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation., and . IEICE Trans. Inf. Syst., 88-D (9): 2135-2142 (2005)Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons., and . Journal of Intelligent and Robotic Systems, 21 (2): 103-115 (1998)Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks., and . DFT, page 177-184. IEEE Computer Society, (1994)Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger., , and . J. Electron. Test., 24 (1-3): 11-19 (2008)