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Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)An 8-Gb/s simultaneous bidirectional link with on-die waveform capture., , , , and . IEEE J. Solid State Circuits, 38 (12): 2111-2120 (2003)A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 40 (1): 233-244 (2005)Analysis of PLL clock jitter in high-speed serial links., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (11): 879-886 (2003)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)Session 10 - Panel discussion Sure, Moore's Law can continue, but should it., , , , , and . CICC, IEEE, (2008)Jitter in high-speed serial and parallel links., , , , and . ISCAS (4), page 425-428. IEEE, (2004)8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew., , , , , , , and . IEEE J. Solid State Circuits, 40 (1): 80-88 (2005)A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS., , , , , , , , and . ISSCC, page 452-453. IEEE, (2008)A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 45 (12): 2828-2837 (2010)