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A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems.

, and . IEEE Trans. Parallel Distributed Syst., 11 (5): 444-458 (2000)

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A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation., and . ICPP (1), page 2-9. CRC Press, (1992)A Parallel Architecture for Optical Computing., and . PPSC, page 414-418. SIAM, (1987)An Approximate Communication Framework for Network-on-Chips., and . IEEE Trans. Parallel Distributed Syst., 31 (6): 1434-1446 (2020)LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs., , , and . DAC, page 82:1-82:6. ACM, (2018)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures., , , and . ASP-DAC, page 1-6. IEEE, (2009)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture., , and . ANCS, page 47-56. ACM, (2007)Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3638-3649 (2020)SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference., , and . HPCA, page 831-845. IEEE, (2022)4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs., , , and . ICECS, page 1-4. IEEE, (2020)Approximate Network-on-Chips with Application to Image Classification., , , and . NAS, page 1-8. IEEE, (2022)