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Disambiguation of "Yoshimura, Takeshi"

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A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix.

, and . DAC, page 653-657. ACM Press, (1995)

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Tateo Yoshimura

Takeshi Morita

Tadasuke Yoshimura

Takeshi Morita

Takeshi Imamura

 

Other publications of authors with the same name

Register placement for high-performance circuits., , and . DATE, page 1470-1475. IEEE, (2009)Double feedback streaming agent for real-time delivery of media over 3G wireless networks., , and . WCNC, page 2102-2106. IEEE, (2003)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing., , , and . IEICE Trans. Electron., 101-C (4): 263-272 (2018)Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis., , and . ASP-DAC, page 237-242. IEEE, (2013)Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair., , and . ISCAS, page 3403-3406. IEEE, (2007)Genetic Algorithm based pipeline scheduling in high-level synthesis., and . ASICON, page 1-4. IEEE, (2013)Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis., , , and . ASICON, page 1-4. IEEE, (2015)Power and resource aware scheduling with multiple voltages., , , , and . ASICON, page 1-4. IEEE, (2013)Floorplanning driven Network-on-Chip synthesis for 3-D SoCs., , , , and . ISCAS, page 1203-1206. IEEE, (2011)Mobility overlap-removal based leakage power aware scheduling in high-level synthesis., , , and . ISCAS, page 1745-1748. IEEE, (2013)