( en | de | ru )

 

Disambiguation of "Jung, Seong-Ook"

Author of the publication

copydeleteadd this publication to your clipboard
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (8): 1508-1517 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

 

Other publications of authors with the same name

Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM., , , , and . ISOCC, page 479-482. IEEE, (2012)A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction., , , and . ESSCIRC, page 181-184. IEEE, (2012)All-digital 90° phase-shift DLL with a dithering jitter suppression scheme., , , , and . CICC, page 1-4. IEEE, (2013)Noise constrained transistor sizing and power optimization for dual Vst domino logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (5): 532-541 (2002)Coupling delay optimization by temporal decorrelation using dual threshold voltage technique., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 879-887 (2003)Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1828-1839 (2019)STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1630-1634 (2014)Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (7): 1428-1441 (2009)Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 1023-1032 (2016)A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 1860-1870 (2012)