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Disambiguation of "Choi, Injun"

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Efficiency evaluation of data warehouse operations.

, , and . Decis. Support Syst., 44 (4): 883-898 (2008)

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Andreas Choi

Bongkyung Choi

Jinsub Choi

Carmen Choi

Jinchul Choi

 

Other publications of authors with the same name

Incorporating the Effects of Organizational Structure into Business Process Simulation., , , and . AP-BPM, volume 181 of Lecture Notes in Business Information Processing, page 132-142. Springer, (2014)A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces., , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3071-3082 (2022)Task net: Transactional workflow model based on colored Petri net., , and . Eur. J. Oper. Res., 136 (2): 383-402 (2002)ProST-re: Simulation-Based Analytics for Finding Appropriate Substitutes and Task Reallocation., , and . IEEE Access, (2022)A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface., , , , and . IEEE J. Solid State Circuits, 54 (10): 2658-2670 (2019)On Resolving Schematic Heterogeneity in Multidatabase Systems., , , and . Distributed Parallel Databases, 1 (3): 251-279 (1993)On Resolving Schematic Heterogeneity in Multidatabase Systems., , , and . Modern Database Systems, ACM Press and Addison-Wesley, (1995)A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation., , , , , , , and . CICC, page 1-2. IEEE, (2022)A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS., , , , , and . CICC, page 1-2. IEEE, (2023)An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)