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Disambiguation of "Sapatnekar, Sachin S."

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ALIGN: Open-Source Analog Layout Automation from the Ground Up.

, , , , , , , , and . DAC, page 77. ACM, (2019)

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Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

 

Other publications of authors with the same name

Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis., , and . ISLPED, page 298-303. ACM, (2006)A survey on multi-net global routing for integrated circuits., and . Integr., 31 (1): 1-49 (2001)Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2104-2117 (2012)BDD decomposition for delay oriented pass transistor logic synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 957-970 (2005)Placement and Routing in 3D Integrated Circuits., , , , , , and . IEEE Des. Test Comput., 22 (6): 520-531 (2005)Book Review: An Assay of Biochips.. IEEE Des. Test Comput., 24 (4): 402-403 (2007)Building your yield of dreams.. IEEE Des. Test Comput., 25 (2): 194-195 (2008)NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (8): 1844-1857 (2020)A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem CMOS gates., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 779-788 (2000)A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (9): 1295-1306 (2009)