( en | de | ru )

 

Disambiguation of "Cazeaux, José Manuel"

Author of the publication

copydeleteadd this publication to your clipboard
Novel on-chip circuit for jitter testing in high-speed PLLs.

, , and . IEEE Trans. Instrum. Meas., 54 (5): 1779-1788 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

José Manuel Cardozo

José-Manuel Rodriguez

Manuel José Morais

José-Manuel Soriano-Romero

José Manuel Gonzalez Fernandez

 

Other publications of authors with the same name

Novel on-chip circuit for jitter testing in high-speed PLLs., , and . IEEE Trans. Instrum. Meas., 54 (5): 1779-1788 (2005)Self-Checking Voter for High Speed TMR Systems., , and . J. Electron. Test., 21 (4): 377-389 (2005)Accurate Linear Model for SET Critical Charge Estimation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1161-1166 (2009)Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation., , , , and . IOLTS, page 17-22. IEEE Computer Society, (2006)Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop., , and . IOLTS, page 17-24. IEEE Computer Society, (2004)The Other Side of the Timing Equation: a Result of Clock Faults., , , , and . DFT, page 169-177. IEEE Computer Society, (2005)Clock Faults Induced Min and Max Delay Violations., , , , and . J. Electron. Test., 30 (1): 111-123 (2014)Fault tolerant techniques for electronic systems implemented by nanometer technology.. University of Bologna, Italy, (2006)On Transistor Level Gate Sizing for Increased Robustness to Transient Faults., , , , and . IOLTS, page 23-28. IEEE Computer Society, (2005)New High Speed CMOS Self-Checking Voter., , and . IOLTS, page 58-66. IEEE Computer Society, (2004)