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Disambiguation of "Garlepp, Bruno W."

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Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.

, , , , , , , , , , , , and . CICC, page 709-716. IEEE, (2005)

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Christoph Garlepp

Bruno W Neu

Paul W Bruno

Bruno W Nikles

Dieter Garlepp

 

Other publications of authors with the same name

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter., , , , , and . ISSCC, page 1276-1285. IEEE, (2006)A new technique for characterization of digital-to-analog converters in high-speed systems., , , , and . DATE, page 433-438. EDA Consortium, San Jose, CA, USA, (2007)A portable digital DLL for high-speed CMOS interface circuits., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 632-644 (1999)1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus., , , , , , and . IEEE J. Solid State Circuits, 36 (5): 752-760 (2001)A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator., , , , , , , , , and 1 other author(s). ISSCC, page 244-245. IEEE, (2010)A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 45 (12): 2566-2581 (2010)A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation., , , and . ISSCC, page 884-893. IEEE, (2006)