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Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures.

, , , and . ARCS Workshops, volume P-81 of LNI, page 142-151. GI, (2006)

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A Concept for an Evaluation Framework for Reconfigurable Systems., and . FPL, volume 1673 of Lecture Notes in Computer Science, page 475-480. Springer, (1999)Mapping basic prefix computations to fast carry-chain structures., and . FPL, page 604-608. IEEE, (2009)Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz., , and . GI-Jahrestagung, volume P-246 of LNI, page 1385-1398. GI, (2015)Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays., , and . FPL, volume 1482 of Lecture Notes in Computer Science, page 411-415. Springer, (1998)Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains., and . FPL, page 318-325. IEEE Computer Society, (2010)Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen., and . MMB (Kurzbeiträge), page 51-58. TU Bergakademie Freiberg, (1997)The Java Virtual Machine in retargetable, high-performance instruction set simulation., , , and . PPPJ, page 21-30. ACM, (2011)Ready PCIe data streaming solutions for FPGAs., and . FPL, page 1-4. IEEE, (2014)Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture., , and . CSOC (3), volume 1226 of Advances in Intelligent Systems and Computing, page 304-313. Springer, (2020)Implementation of Architecture Concepts for Hardware Agent Systems., , and . CIT, page 823-828. IEEE Computer Society, (2007)