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Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks.

, , and . UKSim, page 424-429. IEEE, (2013)

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Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip., , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Low-Latency Asynchronous Logic Design for Inference at the Edge., , , and . CoRR, (2020)REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines., , , , , , and . IEEE Trans. Pattern Anal. Mach. Intell., 45 (9): 11152-11168 (September 2023)Low-Latency Asynchronous Logic Design for Inference at the Edge., , , and . DATE, page 370-373. IEEE, (2021)Synthesis of SI Circuits from Burst-Mode Specifications., , , , and . DATE, page 366-369. IEEE, (2021)Automated Synthesis of Asynchronous Tsetlin Machines on FPGA., , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Memory efficient on-line streaming for multichannel spike train analysis., , , , , and . EMBC, page 2315-2318. IEEE, (2011)Overview study of on-chip interconnect modelling approaches and its trend., , and . MOCAST, page 1-5. IEEE, (2018)Asynchronous design, Quo Vadis?. DDECS, page 3. IEEE Computer Society, (2010)Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets., , , and . PATMOS, page 69-74. IEEE, (2019)