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Disambiguation of "Yamaoka, Masanao"

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Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?

, , , , , , , , , , , , and . VLSIC, page 22-. IEEE, (2015)

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Hideki Yamaoka

So Yamaoka

 

Other publications of authors with the same name

Operating-margin-improved SRAM with column-at-a-time body-bias control technique., and . ESSCIRC, page 396-399. IEEE, (2007)A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems., , , , and . A-SSCC, page 1-3. IEEE, (2021)Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity., , , , , , , , , and . TPNC, volume 11324 of Lecture Notes in Computer Science, page 111-123. Springer, (2018)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , and . CICC, page 701-704. IEEE, (2009)0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme., , and . IEEE J. Solid State Circuits, 39 (6): 934-940 (2004)90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique., , , , , , , and . IEEE J. Solid State Circuits, 41 (3): 705-711 (2006)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , and . Int. J. Netw. Comput., 7 (2): 154-172 (2017)STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 165-178 (2021)A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines., , , , , and . IEICE Trans. Inf. Syst., 102-D (9): 1696-1706 (2019)Efficient Ising Model Mapping to Solving Slot Placement Problem., , , , , , , and . ICCE, page 1-6. IEEE, (2019)