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NeuronFlow: a neuromorphic processor architecture for Live AI applications., , , , , , , , , and 3 other author(s). DATE, page 840-845. IEEE, (2020)Evolutionary multi-level acyclic graph partitioning., , and . J. Heuristics, 26 (5): 771-799 (2020)Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver., , and . DATE, page 1-4. European Design and Automation Association, (2014)Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators., , , , and . CoRR, (2021)Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors., , , and . SAC, page 1517-1524. ACM, (2013)Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis., , , , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 695-706. Springer, (2000)Buffer allocation for real-time streaming on a multi-processor without back-pressure., , and . ESTIMedia, page 20-29. IEEE, (2014)Cyclo-Static Data Flow Model for TDM., , , , and . ACSD, page 82-91. IEEE Computer Society, (2014)Buffer Sizing for Rate-Optimal Single-Rate Data-Flow Scheduling Revisited., , , and . IEEE Trans. Computers, 59 (2): 188-201 (2010)SpArNet: Sparse Asynchronous Neural Network execution for energy efficient inference., , , , and . AICAS, page 256-260. IEEE, (2020)