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A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (1): 156-160 (2021)Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA., , , , and . MCSoC, page 143-150. IEEE Computer Society, (2017)Body Bias Control on a CGRA based on Convex Optimization., , , and . COOL CHIPS, page 1-3. IEEE, (2022)7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2., , , and . FPL, page 1. IEEE, (2015)Flexible Software-Defined Packet Processing Using Low-Area Hardware., , , , , and . IEEE Access, (2020)Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping., , , , , and . HEART, page 13:1-13:6. ACM, (2018)A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control., , and . COOL Chips, page 1-3. IEEE Computer Society, (2015)Body bias control for renewable energy source with a high inner resistance., , and . COOL Chips, page 1-3. IEEE Computer Society, (2017)Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process., , , , and . CANDAR Workshops, page 269-274. IEEE, (2019)Glitch-aware variable pipeline optimization for CGRAs., , , and . ReConFig, page 1-6. IEEE, (2017)