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Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.

, , , , and . SBCCI, page 12:1-12:6. ACM, (2015)

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High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation., , , , , and . LASCAS, page 1-4. IEEE, (2023)Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation., , , , , , , and . SBESC, page 31-38. IEEE Computer Society, (2017)An efficient sub-sample interpolator hardware for VP9-10 standards., , , , , , , and . ICIP, page 2167-2171. IEEE, (2016)Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC., , , , , , and . ISCAS, page 1-5. IEEE, (2020)High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator., , , , , and . J. Real Time Image Process., 16 (1): 175-192 (2019)High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (5): 883-887 (2019)Pareto-based energy control for the HEVC encoder., , , , and . ICIP, page 814-818. IEEE, (2016)Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms., , , , and . SBCCI, page 7. ACM, (2019)Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms., , , , and . ReCoSoC, page 1-8. IEEE, (2019)High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards., , , , , and . ICIP, page 2162-2166. IEEE, (2016)