( en | de | ru )

 

Disambiguation of "Onodera, Hidetoshi"

Author of the publication

copydeleteadd this publication to your clipboard
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias.

, , and . APCCAS, page 31-34. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Perturbation-immune radiation-hardened PLL with a switchable DMR structure., , and . IOLTS, page 128-132. IEEE, (2013)Statistical modeling of gate-delay variation with consideration of intra-gate variability., , and . ISCAS (5), page 513-516. IEEE, (2003)ST: PERL package for simulation and test environment., and . ISCAS (5), page 89-92. IEEE, (2001)A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing., , , , , and . ISVLSI, page 488-493. IEEE, (2020)On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator., and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 183-187 (2014)A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design., and . SoCC, page 315-318. IEEE, (2006)Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2535-2548 (2014)2016 ASP-DAC.. IEEE Des. Test, 33 (3): 133-134 (2016)A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2776-2784 (2017)Statistical Gate Delay Model for Multiple Input Switching., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3070-3078 (2009)