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A new performance-driven global routing algorithm for gate array., , and . VLSI, volume A-42 of IFIP Transactions, page 321-330. North-Holland, (1993)SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits., , and . EURO-DAC, page 142-148. EEE Computer Society, (1991)Performance-Driven Steiner Tree Algorithm for Global Routing., , , , and . DAC, page 177-181. ACM Press, (1993)A Dynamic and Efficient Representation of Building-Block Layout., , and . DAC, page 376-384. IEEE Computer Society Press / ACM, (1987)Basic Circuit Theory, and . Tate McGrawHill, New Delhi, (2010)Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (5): 828-837 (1987)Accurate reduced RL model for frequency dependent transmission lines., and . ICECS, page 761-764. IEEE, (2002)Design methodology of high performance on-chip global interconnect using terminated transmission-line., , , , , , , and . ISQED, page 451-458. IEEE Computer Society, (2009)Floorplanning with Pin Assignment., , and . ICCAD, page 98-101. IEEE Computer Society, (1990)Hierarchical placement for macrocells: a 'meet in the middle' approach., , , and . ICCAD, page 460-463. IEEE Computer Society, (1988)