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Hybrid spiking-stochastic Deep Neural Network.

, , и . VLSI-DAT, стр. 1-4. IEEE, (2017)

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Andreas Choi

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Bongkyung Choi

Jinsub Choi

Carmen Choi

 

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Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign., и . CODES, стр. 3-7. IEEE Computer Society, (1997)Optimizing geographically distributed timed cosimulation by hierarchically grouped messages., и . CODES, стр. 100-104. ACM, (1999)DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture., , и . HPCA, стр. 25-36. IEEE Computer Society, (2014)Energy-efficient partitioning of hybrid caches in multi-core architecture., и . VLSI-SoC, стр. 1-6. IEEE, (2014)Aging Gracefully with Approximation., , , , , и . ISCAS, стр. 1-5. IEEE, (2019)Rate Assignment for Embedded Reactive Real-Time Systems., и . EUROMICRO, стр. 10237-. IEEE Computer Society, (1998)Optimal mapping of program overlays onto many-core platforms with limited memory capacity., , и . Des. Autom. Embed. Syst., 21 (3-4): 173-194 (2017)Binary acceleration using coarse-grained reconfigurable architecture., , и . SIGARCH Comput. Archit. News, 38 (4): 33-39 (2010)Coarse-grained reconfigurable architecture for multiple application domains: a case study., , , , , , и . ICHIT, том 321 из ACM International Conference Proceeding Series, стр. 546-553. ACM, (2009)Critical-path-aware high-level synthesis with distributed controller for fast timing closure., и . ACM Trans. Design Autom. Electr. Syst., 19 (2): 16:1-16:29 (2014)