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High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.

, , and . VLSI Design, page 569-574. IEEE Computer Society, (2006)

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A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs., , , and . VLSI Design, page 130-133. IEEE Computer Society, (2005)RG-SRAM: A Low Gate Leakage Memory Design., , and . ISVLSI, page 295-296. IEEE Computer Society, (2005)DG-SRAM: a low leakage memory circuit., , and . SoCC, page 167-170. IEEE, (2005)Leakage Reduction for Domino Circuits in Sub-65nm Technologies., , and . SoCC, page 164-167. IEEE, (2006)Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits., , and . J. Low Power Electron., 1 (2): 182-193 (2005)Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM).. ISQED, page 8-9. IEEE Computer Society, (2008)Leakage aware SER reduction technique for UDSM logic circuits., , , and . SoCC, page 82-85. IEEE, (2004)Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level., , and . SoCC, page 79-82. IEEE, (2007)High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach., , and . VLSI Design, page 569-574. IEEE Computer Society, (2006)SRAM Local Bit Line Access Failure Analyses., , , , , and . ISQED, page 204-209. IEEE Computer Society, (2006)