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A DSEL for high throughput and low latency software-defined radio on multicore CPUs.

, , , , , and . Concurr. Comput. Pract. Exp., (2023)

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Efficient architecture for Reed Solomon block turbo code., , , , and . ISCAS, IEEE, (2006)Reed-Solomon behavioral virtual component for communication systems., , , , and . ISCAS (4), page 173-176. IEEE, (2004)Softcore Processor Optimization According to Real-Application Requirements., and . IEEE Embed. Syst. Lett., 5 (1): 4-7 (2013)Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis., , , and . SiPS, page 242-247. IEEE, (2019)High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping., , , and . J. Signal Process. Syst., 57 (3): 349-361 (2009)Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes., , , and . J. Signal Process. Syst., 88 (3): 425-438 (2017)FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems.. ERSA, page 9-18. CSREA Press, (2009)A highly parallel Turbo Product Code decoder without interleaving resource., , , , and . SiPS, page 1-6. IEEE, (2008)Stochastic Decoding of Turbo Codes., , , and . IEEE Trans. Signal Process., 58 (12): 6421-6425 (2010)How to Feed a Growing Population - An IoT Approach to Crop Health and Growth., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (3): 435-448 (2021)