( en | de | ru )

 

Disambiguation of "Horita, Tadayoshi"

Author of the publication

copydeleteadd this publication to your clipboard
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.

, , , , and . Trans. Comput. Sci., (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tadayoshi Kohno

 

Other publications of authors with the same name

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays., and . PDPTA, CSREA Press, (2000)Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types., and . PRDC, page 233-240. IEEE Computer Society, (2001)A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults., and . ISPAN, page 16-22. IEEE Computer Society, (1997)Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions., and . IEEE Trans. Computers, 49 (6): 542-552 (2000)Reconfigurable architectures for mesh-arrays with PE and link faults., and . DFT, page 108-116. IEEE Computer Society, (1995)An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron., and . Neurocomputing, (2013)An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications., and . Trans. Comput. Sci., (2011)Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant., , , and . PDPTA, page 546-552. CSREA Press, (2009)A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings., , , , and . MCSoC, page 245-252. IEEE Computer Society, (2014)A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement., and . PRDC, page 96-104. IEEE Computer Society, (2012)