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Parallel Circuit Simulation Using Hierarchical Relaxation.

, , , and . DAC, page 394-399. IEEE Computer Society Press, (1990)

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Exact Evaluation of Diagnostic Test Resolution., , , and . DAC, page 347-352. IEEE Computer Society Press, (1992)Improving Parallel Circuit Simulation Using High-Level Waveforms., , and . ISCAS, page 728-731. IEEE, (1995)An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs., and . IEEE J. Solid State Circuits, 44 (2): 584-593 (2009)A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm., and . ISVLSI, page 103-108. IEEE Computer Society, (2006)Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms., , , and . SoC, page 1-4. IEEE, (2009)Delay macromodeling and estimation for RTL., , and . ISCAS, page 2430-2433. IEEE, (2008)An improved "soft" eFPGA design and implementation strategy., , and . CICC, page 179-182. IEEE, (2005)Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning., , , , and . IEEE Access, (2022)A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers., , and . ISCAS (1), page 173-176. IEEE, (2003)SoC implementation issues for synthesizable embedded programmable logic cores., , , and . CICC, page 45-48. IEEE, (2003)