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Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures.

, , and . ERSA, page 225-231. CSREA Press, (2004)

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Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system., , , and . Scalable Comput. Pract. Exp., (2007)Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing., , , , and . IPDPS, IEEE Computer Society, (2002)Self-configurable architecture for reusable systems with Accelerated Relocation Circuit (SCARS-ARC)., , , and . IPDPS Workshops, page 1-4. IEEE, (2010)A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations., and . FPT, page 291-292. IEEE, (2005)Reconfigurable media processing., and . Parallel Comput., 28 (7-8): 1111-1139 (2002)Lifting kernel-based sprite codec., and . VCIP, volume 4310 of Proceedings of SPIE, page 86-98. SPIE, (2001)Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms., , , , and . IET Comput. Digit. Tech., 4 (2): 126-142 (2010)A survey of media processing approaches., and . IEEE Trans. Circuits Syst. Video Techn., 12 (8): 633-645 (2002)Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications., , and . ERSA, page 296. CSREA Press, (2004)Analysis and Design of a Context Adaptable SAD/MSE Architecture., , and . Int. J. Reconfigurable Comput., (2009)