Author of the publication

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM.

, , , , , and . CoRR, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Novel Linear Walking Type Piezoelectric Actuator Based on the Parasitic Motion of Flexure Mechanisms., , , , , and . IEEE Access, (2019)Extraction of Spatial-Temporal Features of Bus Loads in Electric Grids Through Clustering in a Dynamic Model Space., , , , and . IEEE Access, (2020)Lagrangian relaxation-based routing path allocation for application-specific network-on-chips., , , and . Integr., (2018)Synthesis of custom interleaved memory systems., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 74-83 (2000)Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems., , , and . AICAS, page 238-242. IEEE, (2020)Leakage Power Aware Scheduling in High-Level Synthesis., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (4): 940-951 (2014)Research on neural network optimization algorithm for building energy consumption prediction., , and . J. Comput. Methods Sci. Eng., 18 (3): 695-707 (2018)Exploration of Schedule Space by Random Walk., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (1): 199-212 (2020)Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (8): 1287-1300 (2017)