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Disambiguation of "Takano, Kyoya"

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A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler.

, , , , and . RWS, page 125-127. IEEE, (2022)

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Other publications of authors with the same name

300-GHz-Band OFDM Video Transmission with CMOS TX/RX Modules and 40dBi Cassegrain Antenna toward 6G., , , , , , , , , and 7 other author(s). IEICE Trans. Electron., 104-C (10): 576-586 (2021)Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit., , , , and . IEICE Trans. Electron., 95-C (6): 1077-1085 (2012)Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication., , , , and . IEICE Trans. Electron., 98-C (12): 1091-1104 (2015)A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology., , , , and . IEICE Trans. Electron., 95-C (7): 1154-1162 (2012)98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits., , , , , and . IEEE J. Solid State Circuits, 48 (10): 2273-2284 (2013)39 - 67 GHz CMOS Multistage Power Amplifier With Two-Way Power Stage., , , , and . ICICDT, page 61-63. IEEE, (2023)A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock Range., , , , , and . A-SSCC, page 219-222. IEEE, (2018)A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler., , , , and . RWS, page 125-127. IEEE, (2022)135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS., , , , , and . VLSIC, page 50-51. IEEE, (2012)A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface., , , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 2988-2998 (2022)