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A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS.

, , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (5): 339-343 (2014)

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Yen-Tai Wan

Yen Yen Kwan

Tina Yener

Nazlı Yener Aǧabeyoǧlu

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11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS., , , и . ISSCC, стр. 196-197. IEEE, (2014)A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (5): 339-343 (2014)An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 683-692 (2016)A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS., , и . VLSIC, стр. 92-93. IEEE, (2012)A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (12): 1166-1170 (2016)A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS., , , , и . A-SSCC, стр. 81-84. IEEE, (2014)A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration., , , , и . ISCAS, стр. 1-4. IEEE, (2020)