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Disambiguation of "Takenaka, Hiroyuki"

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Ferroelectric Domain Wall Induced Band Gap Reduction and Charge Separation in Organometal Halide Perovskites

, , , , , and . The Journal of Physical Chemistry Letters, 6 (4): 693--699 (February 2015)
DOI: 10.1021/jz502666j

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Mizuki Takenaka

Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Okamuro

Hiroyuki Takada

 

Other publications of authors with the same name

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive., , , , , and . IEEE J. Solid State Circuits, 34 (11): 1557-1563 (1999)Ferroelectric Domain Wall Induced Band Gap Reduction and Charge Separation in Organometal Halide Perovskites, , , , , and . The Journal of Physical Chemistry Letters, 6 (4): 693--699 (February 2015)First-Principles Calculation of the Bulk Photovoltaic Effect in CH3NH3PbI3 and CH3NH3PbI3--x Cl x, , , , and . The journal of physical chemistry letters, 6 (1): 31--37 (2014)Interface socket design methodology to generate embedded DRAM macros., , , , , , , , , and 5 other author(s). CICC, page 537-540. IEEE, (2001)An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications., , , , , , , , , and 3 other author(s). ISSCC, page 276-277. IEEE, (2008)A 65nm low-power embedded DRAM with extended data-retention sleep mode., , , , , , , , , and 1 other author(s). ISSCC, page 567-576. IEEE, (2006)A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 35 (4): 545-551 (2000)