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Communication Models in Networks-on-Chip.

, , и . IEEE International Workshop on Rapid System Prototyping, стр. 57-60. IEEE Computer Society, (2007)

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Luis Fernando de Moraes y Blanco

Izabel Moraes

Paolo Moraes

Flávia Moraes

Rodrigo Moraes

 

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A Virtual CMOS Library Approach for East Layout Synthesis., , и . VLSI, том 162 из IFIP Conference Proceedings, стр. 415-426. Kluwer, (1999)Congestion-aware task mapping in heterogeneous MPSoCs., и . SoC, стр. 1-4. IEEE, (2008)Current mask generation: a transistor level security against DPA attacks., , , , , , и . SBCCI, стр. 115-120. ACM, (2005)Interconnection Length Estimation at Logic-Level., , и . SBCCI, стр. 98-102. IEEE Computer Society, (2001)LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design., , и . SBCCI, стр. 327-332. IEEE Computer Society, (2000)SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems., , , , и . IEEE International Workshop on Rapid System Prototyping, стр. 27-33. IEEE Computer Society, (2007)Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems., , , , , и . ISCAS, стр. 1-5. IEEE, (2018)Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator., , , , , , , , , и . IET Comput. Digit. Tech., 15 (2): 125-142 (2021)Runtime fault recovery protocol for NoC-based MPSoCs., , , , и . ISQED, стр. 132-139. IEEE, (2014)Flow oriented routing for NOCS., и . SoCC, стр. 367-370. IEEE, (2010)