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Asymmetric-access aware optimization for STT-RAM caches with process variations., , , , and . ACM Great Lakes Symposium on VLSI, page 143-148. ACM, (2013)A frequent-value based PRAM memory architecture., , , and . ASP-DAC, page 211-216. IEEE, (2011)EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond., , , , and . CoRR, (2018)Rapid design space exploration of two-level unified caches., , , and . ISCAS, page 1937-1940. IEEE, (2014)Accelerate context switch by racetrack-SRAM hybrid cells., , and . NANOARCH, page 115-116. ACM, (2016)GRT: A Reconfigurable SDR Platform with High Performance and Usability., , , , , , , and . SIGARCH Comput. Archit. News, 42 (4): 51-56 (2014)Energon: Toward Efficient Acceleration of Transformers Using Dynamic Sparse Attention., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 136-149 (2023)Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface., , , and . ACM Trans. Archit. Code Optim., 10 (4): 24:1-24:25 (2013)Exploring Parameter-Efficient Fine-tuning for Improving Communication Efficiency in Federated Learning., , , and . CoRR, (2022)NXgraph: An Efficient Graph Processing System on a Single Machine., , , , , and . CoRR, (2015)