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Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies., and . ISCAS, IEEE, (2006)Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling., and . SoCC, page 151-154. IEEE, (2005)A design methodology for temperature variation insensitive low power circuits., and . ACM Great Lakes Symposium on VLSI, page 410-415. ACM, (2006)A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells., and . ISCAS, page 2185-2188. IEEE, (2014)2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents., and . ISCAS, page 2932-2935. IEEE, (2015)Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode., , and . Integr., (2016)Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits., and . ICECS, page 1280-1283. IEEE, (2007)Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption., and . ICECS, page 25-28. IEEE, (2013)Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 533-545 (2013)Low Power and High Speed Multi Threshold Voltage Interface Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (5): 638-645 (2009)