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Disambiguation of "Kajihara, Seiji"

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Low Power BIST for Scan-Shift and Capture Power.

, , , , and . Asian Test Symposium, page 173-178. IEEE Computer Society, (2012)

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Seiji Miyashiro

Seiji Osawa

 

Other publications of authors with the same name

Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)A Statistical Quality Model for Delay Testing., , , , and . IEICE Trans. Electron., 89-C (3): 349-355 (2006)Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis., , , and . IEICE Trans. Inf. Syst., 78-D (7): 811-816 (1995)On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test., , , , , , and . IOLTS, page 1-6. IEEE, (2020)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)On compacting test sets by addition and removal of test vectors., , , and . VTS, page 202-207. IEEE Computer Society, (1994)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume., , , and . ICCD, page 387-396. IEEE Computer Society, (2003)Hybrid BIST Using Partially Rotational Scan., , , , and . Asian Test Symposium, page 379-384. IEEE Computer Society, (2001)