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Disambiguation of "Lee, Jaejin"

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Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses.

, , , and . HPCA, page 288-299. IEEE Computer Society, (2004)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Hyemin Lee

Clara Lee

 

Other publications of authors with the same name

Message-passing iterative decoding between detector and RSC code decoder for PMR channel., , , and . IEEE Trans. Consumer Electronics, 54 (4): 1750-1754 (2008)An algorithmic sign-reversing involution for special rim-hook tableaux., and . J. Algorithms, 59 (2): 149-161 (2006)A watermarking sequence using parities of error control coding for image authentication and correction., and . IEEE Trans. Consumer Electronics, 46 (2): 313-317 (2000)HIPS 2019 Keynote.. IPDPS Workshops, page 352. IEEE, (2019)An OpenCL optimizing compiler for reconfigurable processors., , , , , , and . FPT, page 184-191. IEEE, (2013)A convergence of geometric mean for T-related fuzzy numbers., and . Fuzzy Sets Syst., 121 (3): 537-543 (2001)What We Can Learn from the Data: A Multiple-Case Study Examining Behavior Patterns by Students with Different Characteristics in Using a Serious Game., , , and . Technol. Knowl. Learn., 21 (1): 33-57 (2016)A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 55 (1): 167-177 (2020)A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)FA3C: FPGA-Accelerated Deep Reinforcement Learning., , , , and . ASPLOS, page 499-513. ACM, (2019)