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Disambiguation of "Chen, Ming-Shuan"

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A low-PDP and low-area repeater using passive CTLE for on-chip interconnects.

, , and . VLSIC, page 244-. IEEE, (2015)

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Ming Chen

Ming Chen

Ming Chen

Ming Chen

Ming Chen

 

Other publications of authors with the same name

A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS., and . CICC, page 1-4. IEEE, (2014)A low-power highly multiplexed parallel PRBS generator., and . CICC, page 1-4. IEEE, (2012)A 20Gb/s Duobinary Transceiver in 90nm CMOS., , and . ISSCC, page 102-103. IEEE, (2008)A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS., , and . ISSCC, page 38-39. IEEE, (2013)A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology., , and . IEEE J. Solid State Circuits, 50 (3): 763-775 (2015)A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology., and . IEEE J. Solid State Circuits, 50 (8): 1903-1916 (2015)Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data., , and . IEEE J. Solid State Circuits, 43 (9): 2120-2133 (2008)A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection., , and . IEEE J. Solid State Circuits, 48 (11): 2681-2692 (2013)A low-PDP and low-area repeater using passive CTLE for on-chip interconnects., , and . VLSIC, page 244-. IEEE, (2015)A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology., , , , and . IEEE J. Solid State Circuits, 47 (3): 627-640 (2012)