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Disambiguation of "Parries, Paul C."

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Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.

, , , , , , , , , , , , , , , and . IBM J. Res. Dev., (2015)

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Paul C Shields

C L Paul Trüb

Guido C C Clinckspoor

Thomas C C Knöbig

Ullrich C C Jagstaidt

 

Other publications of authors with the same name

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond., , , , , , , , , and 8 other author(s). ICICDT, page 1-4. IEEE, (2012)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., 55 (3): 5 (2011)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)Performance-optimized gate-first 22-nm SOI technology with embedded DRAM., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., (2015)Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation., , , and . ITC, page 1-7. IEEE Computer Society, (2008)